1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing such a semiconductor device, and more particularly to a semiconductor device in a packaged form with a rerouting layer on a semiconductor substrate and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
There have been growing demands for smaller, thinner, and lighter portable electronic devices including digital video cameras, digital mobile phones, and laptop personal computers. To meet the demands, recent semiconductor devices such as VLSI circuits have been scaled down 70 percent in three years. In addition, research and development efforts have been made to perform the important task of increasing the packing density of parts on a mounting board (printed wiring board) in electronic circuit devices wherein semiconductor devices are mounted on printed wiring boards.
Semiconductor device package forms have progressed from the lead-insertion type such as DIP (Dual Inline Package) to the surface-mounted type. There has further been developed a flip-chip mounting process wherein bumps (protrusive electrodes) of solder or gold are disposed on pad electrodes of a semiconductor chip and the semiconductor chip is connected with its face down to a wiring board by the bumps.
Efforts have also been made to develop semiconductor device packages in a complex form called SiP (System in Package) which incorporate passive components such as inductors and capacitors and include matching circuits and filters.
Japanese Patent Laid-Open No. 2003-124236, for example, discloses the structure of a semiconductor device in the SiP form.
If a SiP is packaged in a wafer level, then it is designed to provide a structure in which new interconnects on active components (hereinafter referred to as rerouting) to provide connection to the electrodes of the active components.
If rerouting interconnects are provided as a single layer, then external terminals may not be disposed on the electrodes of the active components. For forming rerouting interconnections to provide a necessary number of I/O ports, then the L/S has to be reduced if a single layer of rerouting interconnects is employed, and hence device design, processes, and materials need to be changed.
Even if the number of I/O ports is sufficient, the number of I/O ports has to be reduced or the I/O ports have to be arrayed in two rows in a peripheral area in order to avoid interference with the electrodes of the active components. As a result, the mounting board has to carry components in a high packing density.
The above problems can be solved by employing two layers of rerouting interconnections. However, the two layers of rerouting interconnections demands insulating layers to be doubled for embedding the interconnections therein, resulting in an increased cost.
Insulating layers to be formed are necessary to be thick enough to fill up steps. The thick insulating layers, however, tends to increase any warpage of the wafer. The increased wafer warpage causes device handling problems in an external electrode forming process, a measuring process, and a thinning process, and the device handling problems are liable to lower the production efficiency.